One chip. Three years. One engineer.
The chip floating behind this page is you. Scroll — and watch yourself get fabricated, layer by layer, from 2nd-year student to placed semiconductor engineer.
Raw silicon holds every possibility.
Your 2nd year deposits the first layer: three awareness workshops, four 15-day FCEP levels and a 30-day Foundation Program — fundamentals before anyone else has started.
Before your batch knows what "fabless" means, you'll have written Verilog.
Every card below is deposited onto your substrate during 2nd year.
Semiconductor Industry & Careers
Global ecosystem, India's Semiconductor Mission, chip design lifecycle, fabless / foundry / OSAT — every career door VLSI opens.
Digital Electronics Fundamentals
Boolean algebra, gates, flip-flops, FSMs, timing — with hands-on logic design lab and simulation demos.
Intro to VLSI & Design Flow
CMOS technology, RTL, verification, PD, DFT — capped with a full RTL-to-GDSII flow demo.
Digital Electronics → CMOS
Logic design and K-maps through MOSFETs, fabrication and standard cell libraries.
RTL with Verilog → Design Flow
Verilog HDL, testbench basics and mini RTL projects — then the complete RTL-to-GDSII picture with FPGA demo.
Semiconductor Foundation Program
Advanced digital, CMOS, RTL & Verilog, Linux, intro to SystemVerilog & UVM, industry standards, mini project.
LOGIC FORMS
Ten modules etch a complete VLSI engineer into the die.
10 modules. 1 complete VLSI engineer.
The exact front-end stack semiconductor companies interview on — plus mini projects: UART · FIFO · SPI · APB · AXI Lite · GPIO.
Advanced Digital Design
FSM, pipelining, memory design, bus architectures, low power.
RTL Design
RTL architecture, coding guidelines, parameterized RTL, arithmetic.
Verilog HDL
Advanced RTL, simulation, debugging, testbench development.
SystemVerilog
Interfaces, packages, assertions, functional coverage, OOP.
UVM
Components, factory, config DB, driver, monitor, scoreboard.
Linux
Commands, shell scripting, development environment setup.
TCL Programming
TCL syntax, tool automation, scripting for EDA tools.
Python for Engineers
Automation, file parsing, report generation.
Static Timing Analysis
Timing paths, constraints, setup & hold, timing reports.
Clock Domain Crossing
Synchronizers, FIFO-based CDC, CDC verification.
Layer 2 Etched — Deliverables
RTL Design Project · Verification Project · UVM Environment · Timing Analysis Assignment · Technical Assessment
3RD YEAR OUTPUTROUTE TO TAPEOUT
DV · PD · DFT. Real projects on RISC-V, Automotive and AI Accelerator IPs — then the 16-step flow every chip must survive.
Scroll to run the full flow.
DV: SystemVerilog · UVM · AXI/AHB/APB | PD: Floorplan → Sign-off | DFT: ATPG · MBIST · LBIST
Real projects: RISC-V · Automotive IP · AI Accelerator RTL — plus internship with Zerlon Semi & partners.
Seven certification layers, deposited one over another.
Each credential stacks on the last — ending in gold.
Certified Semiconductor Explorer
Future Chip Engineer
Certified Semiconductor Foundation Engineer
Certified RTL Design Engineer
Certified Design Verification Engineer
Certified Physical Design Engineer
Industry Ready Semiconductor Engineer
PLACED.
The silicon works. The engineer works. The chip behind you just powered on — and so did your career.
Placement Accelerator: Resume Development · LinkedIn Optimization · Aptitude Training · Technical + HR Interview Prep · Weekly Mock Interviews · Industry Expert Sessions · Opportunities via the Zerlon Network
Enter the Z-SCAP pipeline.
Students from ECE, EEE, E&I, CSE, IT, AI&DS, Robotics, Mechatronics & allied branches — plus faculty and TPOs building a Semiconductor Centre of Excellence at their institution.
📋 Register for Z-SCAP
60 seconds · No obligation · Callback within 24 hours
